View AD5535ABC_1205991.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V
Preliminary Technical Data
FEATURES
High integration: 32-channel, 14-bit DAC with integrated, high voltage output amplifier Guaranteed monotonic Housed in 15 x 15 mm CSP-BGA package Full-scale output voltage programmable from 50 V to 200 V via reference input 700 A drive capability Integrated silicon diode for temperature monitoring DSP-/microcontroller-compatible serial interface Channel update rate: 1.2 MHz Asynchronous RESET facility Temperature range: -10C to +85C
AD5535
GENERAL DESCRIPTION
The AD5535 is a 32-channel, 14-bit DAC with an on-chip high voltage output amplifier. This device is targeted for optical micro-electromechanical systems. The output voltage range is programmable via the REFIN pin. Output range is 0 V to 50 V with REFIN = 1 V and is 0 V to 200 V with REFIN = 4 V. Each amplifier can source 700 A, which is ideal for the deflection and control of optical MEMS mirrors. The selected DAC register is written to via the 3-wire interface. The serial interface operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. The device is operated with AVCC = 4.75 to 5.25 V, DVCC = 2.7 V to 5.25 V, V- = -4.75 V to -5.25 V, V+ = +4.75 V to +5.25 V, VPP = 210 V. REF_IN is buffered internally on the AD5535 and should be driven from a stable reference source.
APPLICATIONS
Optical micro-electromechanical systems (MEMS) Optical cross-point switches Micropositioning applications using Piezo Flextures Level setting in automotive test and measurement
FUNCTIONAL BLOCK DIAGRAM
DVCC AVCC REF_IN VPP PGND V- V+
RESET
ANODE
AD5535
CATHODE DAC R1 RF 14-BIT BUS DAC R1 RF VOUT0
DAC_GND
VOUT1
DAC AGND
R1 RF
VOUT30
DAC DGND INTERFACE CONTROL LOGIC
R1 RF
VOUT31
SCLK
DIN
SYNC
Figure 1.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
05068-001
AD5535 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 9 Typical Performance Characteristics ........................................... 10 Functional Description .................................................................. 11 Digital-to-Analog Section ......................................................... 11 Reset Function ............................................................................ 11 Serial Interface ............................................................................ 11
Preliminary Technical Data
Microprocessor Interfacing....................................................... 11 Applications Information .............................................................. 13 MEMS Mirror Control Application......................................... 13 AD5535 Board Layout to Ensure Compliance with IPC-221 Specification................................................................................ 13 Power Supply Sequencing and Decoupling Recommendations ....................................................................................................... 14 Guidelines for Printed Circuit Board Layout ......................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
10/04--Revision PrE: Preliminary Version
Rev. PrE | Page 2 of 16
Preliminary Technical Data SPECIFICATIONS
AD5535
VPP = 210 V, V- = -5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V; all outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter DC PERFORMANCE Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Zero Code Voltage Offset Error Offset Drift Voltage Gain Gain Temperature Coefficient Channel-to-Channel Gain Match Full-Scale Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Range3 Output Impedance Resistive Load4, 5 Capacitive Load4 Short-Circuit Current DC Crosstalk4 DC Power Supply Rejection (PSRR), VPP AC CHARACTERISTICS Settling Time 1/4 to 3/4 Scale Step 1 LSB Step Slew Rate -3 dB Bandwidth Output Noise Spectral Density 0.1 Hz to 10 Hz Output Noise Voltage Digital-to-Analog Glitch Impulse Digital Crosstalk Analog Crosstalk Digital Feedthrough VOLTAGE REFERENCE, REF_IN6 Input Voltage Range4 Input Current TEMPERATURE MEASUREMENT DIODE4 Peak Inverse Voltage, PIV Forward Diode Drop, VF Forward Diode Current, IF VF Temperature Coefficient, TC 5 TBD TBD TBD TBD 13 TBD 1 4.096 1 5 0.8 2 -1.44
1
Min
A Grade2 Typ 14 0.1 0.5
Max
Unit Bits % of FSR LSB V mV LSB/C V/V ppm/C % ppm/C V M pF mA LSB dB
Conditions/Comments
-45 47.5 0.09 50 TBD 5 8
1 2 +45 52.5
Guaranteed monotonic
0 50 1
VPP - 10
200 0.7 3 70
30 100 10 10 10 3
s s s s V/s V/s kHz nV/Hz V p-p nV-s typ nV-s typ V-s typ nV-s typ V A V V mA mV/C
No load 200 pF load No load 200 pF load No load 200 pF load Measured at 1 kHz 1 LSB change around major carry
AVCC must exceed REFIN by 1.25 V min
Cathode to anode IF = 2 mA, anode to cathode Anode to cathode IF = 250 A
Rev. PrE | Page 3 of 16
AD5535
Parameter DIGITAL INPUTS4 Input Current Input Low Voltage Input High Voltage Input Hysteresis (SCLK and SYNC only) Input Capacitance POWER-SUPPLY VOLTAGES VPP V- V+ AVCC DVCC POWER-SUPPLY CURRENTS7 IPP I- I+ AICC DICC POWER DISSIPATION7
1
Preliminary Technical Data
Min A Grade2 Typ 5 2.0 200 10 (50 x REF_IN) +10 -5.25 4.75 4.75 2.7 210 225 -4.75 5.25 5.25 5.25 110 3.5 3.5 20 0.5 Max 10 0.8 Unit A V V mV pF V V V V V A/channel mA mA mA mA mW Conditions/Comments
DVCC = 3 V to 5 V DVCC = 3 V to 5 V
75 2.5 2.5 16 0.1 609
1 2
See Terminology. A Grade temperature range: -10C to +85C; typically +25C. 3 Linear output voltage range: +7 V to VPP - 10 V. 4 Guaranteed by design and characterization, not production tested. 5 Ensure that TJ max is not exceeded. See the Absolute Maximum Ratings section. 6 Reference input determines output voltage range. Using a 4.096 V reference (REF 198) gives an output voltage range of 0 V to 200 V. Output range is programmable via the reference input. The full-scale output range is programmable from 50 V to 200 V. The linear output voltage range is restricted from 7 V to VPP - 10 V. 7 Outputs unloaded.
Rev. PrE | Page 4 of 16
Preliminary Technical Data
TIMING CHARACTERISTICS
AD5535
VPP = 210 V, V- = -5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V. All specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter1, 2, 3 fUPDATE fCLKIN t1 t2 t3 t4 t5 t6 t7 t8 t9 A Grade 1.2 30 13 13 15 50 10 10 5 200 20 Unit MHz max MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments Channel Update Rate SCLK Frequency SCLK High Pulse Width SCLK Low Pulse Width SYNC Falling Edge to SCLK Falling Edge Setup Time SYNC Low Time SYNC High Time DIN Setup Time DIN Hold Time 19th SCLK Falling Edge to SYNC Falling Edge for Next Write RESET Pulse Width
1 2
See timing diagrams in Figure 2. Guaranteed by design and characterization, not production tested. 3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
t1
SCLK 1 2 3 4 5 16 17 18 19 1
t3 t5
SYNC
t2
t4
t6 t7
t8
DIN MSB LSB
RESET
t9
Figure 2. Serial Interface Timing Diagram
Rev. PrE | Page 5 of 16
05068-002
AD5535 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VPP to AGND V- to AGND V+ to AGND AVCC to AGND, DAC_GND DVCC to DGND Digital Inputs to DGND REF_IN to AGND, DAC_GND VOUT 0-31 to AGND Anode/Cathode to AGND, DAC_GND AGND to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) 124-Lead CSP-BGA Package, JA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Rating 0.3 V to 225 V +0.3 V to -6 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to DVCC + 0.3 V -0.3 V to AVCC + 0.3 V V- to VPP -0.3 V to +7 V -0.3 V to +0.3 V -10C to +85C -65C to +150C 150C 40C/W
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Transient currents up to 100 mA do not cause SCR latch-up. This device is a voltage-integrated circuit with an ESD rating of <2 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly.
220C 10 s to 40 s
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrE | Page 6 of 16
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1234 A B C D E F G H J K L M N P 1234 56 7 8 9 10 11 12 13 14 56 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P
05068-003
AD5535
Figure 3. Pin Configuration
Table 4. 124-Lead CSP-BGA Ball Configuration
CSP-BGA Number A1 A2 A4 A6 A8 A10 A12 A14 B1 B3 B5 B7 B9 B11 B13 C2 C12 Ball Name N/C VOUT 1 VOUT 7 VOUT 11 VOUT 16 VOUT 20 VOUT 25 N/C VOUT 0 VOUT 4 VOUT 9 VOUT 13 VOUT 17 VOUT 21 VOUT 26 VOUT 3 VOUT 22 CSP-BGA Number C14 D1 D13 E2 E4 E6 E8 E10 E12 E14 F3 F5 F7 F9 F13 G14 H1 Ball Name VOUT 29 VOUT 2 VOUT 23 VOUT 5 VOUT 8 VOUT 12 VOUT 15 VOUT 19 VOUT 24 VOUT 31 VOUT 6 VOUT 10 VOUT 14 VOUT 18 VOUT 30 VOUT 28 VPP CSP-BGA Number H2 H13 J3-J12 K1 K2 K3-K14 L1 L2 L3-L13 L14 M1 M2 M3-12 M13 M14 N1 N2 Ball Name VPP VOUT 27 AGND V+ V+ AGND V- V- AGND DAC_GND AGND AGND AGND AVCC AVCC PGND PGND CSP-BGA Number N3 N4 N5-N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11-P13 P14 Ball Name CATHODE ANODE AGND N/C REF_IN DAC_GND RESET DVCC DGND TEST DIN SCLK SYNC AGND N/C
Rev. PrE | Page 7 of 16
AD5535
Table 5. Pin Function Descriptions
Pin AGND AVCC VPP V+ V- PGND DGND DVCC DAC_GND REF_IN VOUT (0-31) ANODE CATHODE SYNC SCLK1 DIN1 TEST
Preliminary Technical Data
Function Analog GND Pins. Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. Output Amplifier High Voltage Supply. Voltage range from (REF_IN x 50) + 10 V to 225 V. V+ Amplifier Supply Pins. Voltage range from 4.75 V to 5.25 V. V- Amplifier Supply Pins. Voltage range from -4.75 V to -5.25 V. Output Amplifier Ground Reference Pins. Digital GND Pins. Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. Reference GND Supply for All the DACs. Reference Voltage for Channels 0-31. Reference input range is 1 V to 4 V and can be used to program the full-scale output voltage from 50 V to 200 V. Analog Output Voltages from the 32 Channels. Anode of Internal Diode for Diode Temperature Measurement. Cathode of Internal Diode for Diode Temperature Measurement. Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds of up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Allows the same data to be simultaneously loaded to all channels of the AD5535. This pin is used for calibration purposes when loading zero scale and full scale to all channels. To invoke this feature, take the TEST pin high. In normal operation, TEST should be tied low. Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions. Zero code is loaded to the DACs.
RESET1
1
Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.
Rev. PrE | Page 8 of 16
Preliminary Technical Data TERMINOLOGY
Integral Nonlinearity (INL) A measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed as a percentage of full-scale range. Differential Nonlinearity (DNL) The difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of 1 LSB maximum ensures monotonicity. Zero-Code Voltage A measure of the output voltage present at the device output with all 0s loaded to the DAC. It includes the offset of the DAC and the output amplifier. It is expressed in V. Offset Error Calculated by taking two points in the linear region of the transfer function, drawing a line through these points, and extrapolating back to the Y axis. It is expressed in mV. Voltage Gain Calculated from the change in output voltage for a change in code multiplied by 16,384 and divided by the REF_IN voltage. This is calculated between two points in the linear section of the transfer function. Gain Error A measure of the output error with all 1s loaded to the DAC, and is the difference between the ideal and actual analog output range. Ideally, the output should be 50 x REF_IN. It is expressed as a percentage of full-scale range. DC Power-Supply Rejection Ratio (PSRR) A measure of the change in analog output for a change in VPP supply voltage. It is expressed in dB. VPP is varied 5%. DC Crosstalk The dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and the output change of all other DACs. It is expressed in LSB.
AD5535
Output Temperature Coefficient A measure of the change in analog output with changes in temperature. It is expressed in ppm/C. Output Voltage Settling Time The time taken from when the last data bit is clocked into the DAC until the output has settled to within 0.5 LSB of its final value. Digital-to-Analog Glitch Impulse The area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-s, when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). Digital Crosstalk The glitch impulse transferred to the output of one DAC at midscale while a full-scale code change (all 1s to all 0s and vice versa) is being written to another DAC. It is expressed in nV-s. Analog Crosstalk The area of the glitch transferred to the output (VOUT) of one DAC due to a full-scale change in the output (VOUT) of another DAC. The area of the glitch is expressed in nV-s. Digital Feedthrough A measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to (SYNC is high). It is specified in nV-s and is measured with a worst-case change on the digital input pins, for example, from all 0s to all 1s and vice versa. Output Noise Spectral Density A measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per Hz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/(Hz)1/2.
Rev. PrE | Page 9 of 16
AD5535 TYPICAL PERFORMANCE CHARACTERISTICS
16 VOUT = 50V 12 8 4 0 -4 -8 -12 -16 0 2048 4096 6144 8192 10240 12288 CODE
DNL ERROR (LSB) INL ERROR (LSB)
Preliminary Technical Data
1.00 VOUT = 200V 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 2048 4096 6144 8192 10240 12288 INPUT CODE
05068-004
14336 16384
14336 16384
Figure 4. Integral Linearity with VPP = 60 V, VOUT Full Scale = 50 V
1.00 VOUT = 50V 0.75 0.50
DNL ERROR (LSB) DNL ERROR (LSB)
Figure 7. DNL with VPP = 210 V, VOUT Full Scale = 200 V
1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 CH1 5V 0 2048 T
05068-008
0.25 0 -0.25 -0.50 -0.75 -1.00 0 2048 4096 6144 8192 10240 12288 INPUT CODE
05068-005
14336 16384
CH2 5V 6144 8192 10240 12288 14336 16384 M 500ns CH1 21.6V 4096 INPUT CODE
Figure 5.DNL with VPP = 60 V, VOUT Full Scale = 50 V
16 VOUT = 200V 12 8
DNL ERROR (LSB) INL ERROR (LSB)
Figure 8. Short-Circuit Current Limit Timing
1.00 0.75 T 0.50 0.25
2 0
4 0 -4 -8 -12 -16 0 2048 4096 6144 8192 10240 12288 INPUT CODE
T
-0.25 -0.50 1 -0.75 -1.00 CH1 50V 0 2048
05068-006
14336 16384
CH2 200mV M 10s 4096 6144 8192 10240 12288 CH1 14336 83V 16384 INPUT CODE
Figure 6. Integral Linearity with VPP = 210 V, VOUT Full Scale = 200 V
Figure 9. Worst-Case Adjacent Channel Crosstalk
Rev. PrE | Page 10 of 16
05068-009
05068-007
Preliminary Technical Data FUNCTIONAL DESCRIPTION
The AD5535 consists of 32 14-bit DACs with 200 V high voltage amplifiers in a single 15 mm x 15 mm CSP-BGA package. The output voltage range is programmable via the REFIN pin. Output range is 0 V to 50 V with REFIN = 1 V, and 0 V to 200 V with REFIN = 4 V. Communication to the device is through a serial interface operating at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. A 5-bit address and a 14-bit data-word are loaded into the AD5535 input register via the serial interface. The channel address is decoded, and the data-word is converted into an analog output voltage for this channel. At power-on, all the DAC registers are loaded with 0s.
AD5535
A4 to A0 Bits
These bits can address any one of the 32 channels. A4 is the MSB of the address; A0 is the LSB.
DB13 to DB0 Bits
These bits are used to write a 14-bit word into the addressed DAC register. Figure 2 is the timing diagram for a serial write to the AD5535. The serial interface works with both a continuous and a discontinuous serial clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. Any further edges on SYNC are ignored until the correct number of bits are shifted in. Once 19 bits have been shifted in, the SCLK is ignored. For another serial transfer to take place, the counter must be reset by the falling edge of SYNC. The user must allow 200 ns (minimum) between successive writes.
A4 A3 A2 A1 A0 DB13-DB0
05068-010
DIGITAL-TO-ANALOG SECTION
The architecture of each DAC channel consists of a resistor string DAC followed by an output buffer amplifier operating with a nominal gain of 50. The voltage at the REF_IN pin provides the reference voltage for the corresponding DAC. The input coding to the DAC is straight binary and the ideal DAC output voltage is given by
MSB
LSB
VOUT =
50 x VREF _ IN x D 214
Figure 10. Serial Data Format
where D is the decimal equivalent of the binary code, which is loaded to the DAC register (0 to 16,383). The output buffer amplifier is specified to drive a load of 1 M and 200 pF. The linear output voltage range for the output amplifier is from 7 V to VPP - 10V. The amplifier output bandwidth is typically 5 kHz, and is capable of sourcing 700 A and sinking 2.8mA. Settling time for a full-scale step is typically 30 s with no load and 110 s with a 200 pF load.
MICROPROCESSOR INTERFACING
AD5535 to ADSP-21xx Interface
The ADSP-21xx family of DSPs is easily interfaced to the AD5535 without the need for extra logic. A data transfer is initiated by writing a word to the TX register after the SPORT has been enabled. In a write sequence, data is clocked out on each rising edge of the DSP's serial clock and clocked into the AD5535 on the falling edge of its SCLK. The easiest way to provide the 19-bit data-word required by the AD5535, is to transmit two 10-bit data-words from the ADSP-21xx. Ensure that the data is positioned correctly in the TX register so that the first 19 bits transmitted contain valid data. Set up the SPORT control register as follows: TFSW = 1, Alternate Framing INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data ISCLK = 1, Internal Serial Clock TFSR = 1, Frame Every Word ITFS = 1, Internal Framing Signal SLEN = 1001, 10-Bit Data Word Figure 11 shows the connection diagram.
RESET FUNCTION
The reset function on the AD5535 can be used to reset all nodes on the device to their power-on reset condition. All the DACs are loaded with 0s and all registers are cleared. The reset function is implemented by taking the RESET pin low.
SERIAL INTERFACE
The serial interface is controlled by three pins: * * * SYNC is the frame synchronization pin for the serial interface. SCLK is the serial clock input. This pin operates at clock speeds of up to 30 MHz. DIN is the serial data input. Data must be valid on the falling edge of SCLK.
To update a single DAC channel, a 19-bit data-word is written to the AD5535 input register.
Rev. PrE | Page 11 of 16
AD5535
AD5535*
SCLK DIN SYNC *ADDITIONAL PINS OMITTED FOR CLARITY
Preliminary Technical Data
ADSP-2101/ ADSP-2103*
SCLK DT
05068-011
AD5535 to PIC16C6X/7X
The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5535. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is transmitted MSB first. It is important to left-justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. RA1 must be pulled low to start a transfer. It is taken high and pulled low again before any further write cycles can take place. Figure 13 shows the connection diagram.
AD5535*
SCLK DIN SYNC *ADDITIONAL PINS OMITTED FOR CLARITY
TFS
Figure 11. AD5535 to ADSP-2101/ADSP-2103 Interface
AD5535 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)--see the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5535 and the MOSI output drives the serial data line (DIN) of the AD5535. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5535, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. The 68HC11 transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is transmitted MSB first. It is important to left-justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. PC7 must be pulled low to start a transfer. It is taken high and pulled low again before any further write cycles can take place. See Figure 12.
AD5535*
SCLK DIN SYNC *ADDITIONAL PINS OMITTED FOR CLARITY
PIC16C6x/7x*
SCK/RC3 SDI/RC4
05068-013
RA1
Figure 13. AD5535 to PIC16C6x/7x Interface
AD5535 to 8051
The AD5535 requires a clock synchronized to the serial data. The 8051 serial interface must, therefore, be operated in Mode 0. In this mode, serial data exits the 8051 through RxD, and a shift clock is output on TxD. The SYNC signal is derived from a port line (P1.1). Figure 14 shows how the 8051 is connected to the AD5535. Because the AD5535 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. Note also that the AD5535 requires its data with the MSB first. Because the 8051 outputs the LSB first, the transmit routine must take this into account.
AD5535*
SCLK DIN SYNC *ADDITIONAL PINS OMITTED FOR CLARITY TxD RxD
05068-014
MC68HC11*
SCK MOSI
05068-012
PC7
Figure 12. AD5535 to MC68HC11 Interface
8051*
P1.1
Figure 14. AD5535 to 8051 Interface
Rev. PrE | Page 12 of 16
Preliminary Technical Data APPLICATIONS INFORMATION
MEMS MIRROR CONTROL APPLICATION
The AD5535 is targeted to all optical switching control systems based on micro-electromechanical systems (MEMS) technology. The AD5535 is a 32-channel, 14-bit DAC with integrated high voltage amplifiers. The output amplifiers are capable of generating an output range of 0 V to 200 V when using a 4 V reference. The full-scale output voltage is programmable from 50 V to 200 V using reference voltages from 1 V to 4V. Each amplifier can output 700 A and directly drives the control actuators, which determine the position of MEMS mirrors in optical switch applications. The AD5535 is generally used in a closed-loop feedback system, as shown in Figure 15, with a high resolution ADC and DSP. The exact position of each mirror is measured using capacitive sensors. The sensor outputs are multiplexed using an ADG739 to an 8-channel 14-bit ADC (AD7856). An alternative solution is to multiplex using a 32-to-1 multiplexer (ADG732) into a single-channel ADC (AD7671). The control loop is driven by an ADSP-21065L, a 32-bit SHARC DSP with an SPI-compatible SPORT interface. With its 14-bit monotonic behavior and 0 V to 200 V output range coupled with its fast serial interface, the AD5535 is ideally suited for controlling a cluster of MEMSbased mirrors.
REF198 +5V +210V (4.096V) OUTPUT RANGE 0V TO 200V V+ VPP REF_IN 14-BIT DAC VO1 ACTUATORS FOR MEMS MIRROR ARRAY SENSOR + 4 TO 1 MUX (ADG739) OR 32 TO 1 MUX (ADG732) V-
AD5535
8-CHANNEL ADC (AD7856) OR SINGLE CHANNEL ADC (AD7671)
14-BIT DAC
VO32
AD5535
ADSP21065L
Figure 15. AD5535 in a MEMS-Based Optical Switch
AD5535 BOARD LAYOUT TO ENSURE COMPLIANCE WITH IPC-221 SPECIFICATION
The diagram in Figure 16 is a typical 2-layer printed circuit board layout for the AD5535 complying with the specifications outlined in IPC221. The four corner balls labeled as original noconnects must remain, because no connections and no signals should be connected to these balls. Balls labeled as additional no-connects should be connected to AGND. The routing shown in Figure 16 shows the feasibility of connecting to the high voltage balls while complying with the spacing requirements of IPC-221. Figure 17 shows the physical distances that are available.
A1 BALL PAD CORNER 1 1234 56 7 8 9 10 11 12 13 14 A B C D ORIGINAL NO-CONNECTS ADDITIONAL NO-CONNECTS E F G H J K L 1 M N P 1 1 SPACE = 433m 100m SPACE = 433m 250m RAD
05068-016
1.414mm
DETAIL A
250m RAD SPACE = 433m 100m 2mm
Figure 16. Layout Guidelines to Comply with IPC-221
Rev. PrE | Page 13 of 16
05068-015
-5V
m m 5 5 D 40 AD 40 A = = R R E E m C C m A A 0 0 25 SP m SP 25 0 10
AD5535
POWER SUPPLY SEQUENCING AND DECOUPLING RECOMMENDATIONS
The diagram in Figure 17 shows the recommended decoupling, and power supply protection for the AD5535. On the AD5535 it is recommended that all grounds be tied together as close to the device as possible. All supplies should be brought back separately and a provision be made on the board via a link option to drive the AVCC and V+ from the same supply if required to reduce the number of supplies. All power supplies should be adequately decoupled with 10 uF tantalum and 0.1 uF ceramic capacitors. Note that the capacitors on the VPP supply must be rated at greater than 210 V. To overcome issues associated with power supply sequencing when using high voltage supplies, the use of protection diodes as indicated in Figure 17 is recommended.
V- = -5V V+ = +5V VPP = +210V 10F SCHOTTKY DIODE MFTR: ITT 0.1F SD103C PGND AGND DACGND AVCC 10F AVCC = +5V 0.1F V- V+ 0.1F RS1G 10F VPP 0.1F 10F HIGH VOLTAGE DIODE MFTR: GS
Preliminary Technical Data
shield and increase the signal-to-noise performance of the converters by reducing the amount of high frequency digital coupling. Avoid running digital lines under the device, because they couple noise onto the die. The ground plane should be allowed to run under the IC to avoid noise coupling. As large a trace as possible should be used for the supply lines to the device to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near analog inputs of devices. Avoid crossovers of digital and analog signals. Traces for analog inputs should be kept as wide and as short as possible and should be shielded with analog ground where possible. Traces on opposite sides of a 2-layer printed circuit board should run at right angles to each other to reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Multilayer printed circuit boards with dedicated ground, power, and tracking layers offer the optimum solution in terms of obtaining analog performance but at increased manufacturing costs. Good decoupling is vitally important when using high resolution converters. All analog supplies should be decoupled with 10 F tantalum in parallel with 0.1 F ceramic capacitors to analog ground. To achieve the best from the decoupling components, these have to be placed as close to the device as possible ideally right up against the IC or IC socket. The main aim of a bypassing element is to maximize the charge stored in the bypass loop while simultaneously minimizing the inductance of this loop. Inductance in the loop acts as an impedance to high frequency transients and results in power supply spiking. By keeping the decoupling as close to the device as possible, the loop area is kept as small as possible, thereby reducing the possibility of power-supply spikes. Digital supplies of high resolution converters should be decoupled with 10 F tantalum and 0.1 F ceramic to the digital ground plane. VDD and VSS supplies of amplifiers should be decoupled again with 10 F and 0.1 F to AGND. All logic chips should be decoupled with 0.1F to digital ground to decouple high frequency effects associated with digital circuitry.
AD5535
DGND DVCC 10F DVCC = +5V
05068-017
0.1F
Figure 17. Recommended Power Supply Sequencing and Decoupling
GUIDELINES FOR PRINTED CIRCUIT BOARD LAYOUT
Printed circuit boards should be designed such that the analog and digital sections are separated and confined to designated analog and digital sections of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally found to be the best for ground planes, because this optimizes shielding of sensitive signal lines. Digital and analog grounds planes should be joined only in one place, at the AGND and DGND pins of the high resolution converter. Data and address busses on the board should be buffered or latched to isolate the high frequency bus of the processor from the bus of the high-resolution converters. These act as a faraday
Rev. PrE | Page 14 of 16
Preliminary Technical Data OUTLINE DIMENSIONS
15.00 BSC SQ A1 CORNER INDEX AREA
14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P
AD5535
TOP VIEW
DETAIL A 1.70 MAX
1.00 BSC BOTTOM VIEW
DETAIL A
*0.41
*1.25 MAX 0.85 MIN
*COMPLIANT WITH JEDEC STANDARDS MO-192-AAE-1 EXCEPT FOR DIMENSIONS INDICATED BY A "*" SYMBOL. NOMINAL BALL SIZE IS REDUCED FROM 0.60mm TO 0.46mm.
0.36 0.31 *0.46 NOM BALL DIAMETER SEATING PLANE 0.12 NOM COPLANARITY
Figure 18. 124-Lead CSB-BGA Package [CSP-BGA] (BC-124) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5535ABC Function 32 DACs Output Voltage Span 0 to 200 V maximum Temperature Range -10C to +85C Package Description 124-Lead CSP-BGA Package Option BC-124
Rev. PrE | Page 15 of 16
AD5535 NOTES
Preliminary Technical Data
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05068-0-10/04(PrE)
Rev. PrE | Page 16 of 16

▲Up To Search▲

Price & Availability of AD5535ABC

	To Download AD5535ABC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .